1. Field of the Invention
The present invention relates to technology for non-volatile storage.
2. Description of the Related Art
Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397, titled “Source Side Self Boosting Technique For Non-Volatile Memory,” and in U.S. Patent Application Publication 2005/0024939, titled “Detecting Over Programmed Memory,” both of which are incorporated herein by reference in their entirety.
Typically, the program voltage applied to the control gate during a program operation is applied as a series of pulses. In one embodiment, the magnitude of the pulses is increased with each successive pulse by a predetermined step size. In the periods between the program pulses, verify operations are carried out. For arrays of multi-state flash memory cells, the memory cells may perform a verification step of each state to allow a determination of whether the memory cell has reached its target level. For example, a multi-state memory cell capable of storing data in four states may need to perform verify operations for three compare points.
The magnitude of the initial program pulse is typically set during the manufacturing or testing phase using a process called trimming. A part is programmed multiple times, each time using a different magnitude for the initial program pulse. When a particular magnitude for the initial program pulse results in a successful programming of the part, then the part is configured to use that magnitude for the initial program pulse during user operation.
The choice of the magnitude of the program voltage is a compromise. Too high of a value will result in some memory cells being over-programmed, while too low of a value will result in longer programming times. Typically, users of non-volatile memory desire that the memory program quickly.
In some prior art devices, the same program signal is used for new devices that have not been significantly used (also called fresh devices) as well as heavily used devices. However, as a non-volatile memory device undergoes many programming cycles, charge becomes trapped in the insulation between the floating gate and the channel region. This trapping of charge shifts the threshold voltage to a higher level, which allows the memory cell to program quicker. If the magnitude of the program signal is set too high, even though it does not result in over programming of a fresh device, as that device becomes more heavily used then that device may experience over programming. Thus, new devices will have their program voltage set low enough to avoid over programming when the device is older. This lowering of the magnitude of the program voltage will reduce the speed at which the fresh device programs data.
Additional factors that have made it difficult to optimize the magnitude of the program voltage include temperature, back pattern, wafer variations, lot variations, wafer/lot/chip positions, and other factors.